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Vu, H.-G. and Nakada, T. and Nakashima, Y. (2021) Efficient hardware task migration for heterogeneous FPGA computing using HDL-based checkpointing. Integration, 77. pp. 180-192. ISSN 1679260

Thi, H.P. and Lee, H. and Pham, X.N. (2019) Half-row modified two-extra-column trellis min-max decoder architecture for nonbinary LDPC codes. Integration, 69. pp. 234-241. ISSN 1679260

Tran, V.-T. and Trinh, Q.-K. and Hoang, V.-P. (2022) A robust Euclidean metric based ID extraction method using RO-PUFs in FPGA. Integration, 82. pp. 37-47. ISSN 1679260