Mapping Boolean Functions onto Lookup-Tables on FPGAs

This paper presents a lookup-table sharing scheme for implementing Boolean functions on Xilinx FPGAs. The scheme aims to exploit each LUT6 primitive on FPGAs as two Boolean functions sharing five input variables. The proposed algorithm searches for sets of five input variables appearing most frequently in the prime implicants of the Boolean function. These sets are then selected for mapping onto the shared five inputs of the two LUT5s inside an LUT6. The synthesis results on Vivado for Xilinx Virtex 7 show that our mapping scheme achieves better hardware resource utilizations in many cases compared to the non-mapping designs. Our proposals also achieve higher maximum clock frequencies on FPGAs than the non-mapping design for the complex Boolean functions. © 2022 IEEE.