Boolean-Function-based IP Lookup on FPGAs

This paper presents a new approach to IP address lookup based on Boolean functions. Specifically, our method considers an IP address lookup system as a set of Boolean functions sharing a set of input variables. The output vector of such functions indicates the identifier of the input IP address. We then propose a mapping scheme to use each LUT6 as two LUT5s to implement two 5-input Boolean functions, thus increasing the resource efficiency in the IP address lookup systems. Finally, we propose an algorithm for partially mapping Boolean operations onto LUT5s on FPGA. The synthesis results on a Xilinx Artix-7 device show that our mapping scheme brings a much higher hardware efficiency, compared to the non-mapping scheme. Our scheme can save up to 50 of LUT consumption compared with the non-mapping scheme. Compared to the latest prior work, which also implements IP address lookup systems by LUTs, our approach achieves hardware resource efficiency 5x better than Binary content-addressable memory (BiCAM) while keeping the same latency. © 2023 IEEE.