A Novel Efficient Hardware Implementation of Symbol Timing and Carrier Phase Synchronizer for QPSK Receivers

This paper presents an effective hardware design for symbol timing and carrier phase synchronizer in a QPSK SDR receiver intended for implementation on an FPGA. The joint synchronization model is meticulously constructed based on previously established theories. We have made several improvements to the carrier phase synchronizer to enhance its performance. The functionality of the joint synchronizer is initially tested through MATLAB simulations. Subsequently, we perform hardware design, optimizing and accelerating it to achieve high clock speeds and efficient resource utilization. Finally, we implement the hardware design on an FPGA device, specifically the Xilinx XC7A35T, and verify its performance with an actual QPSK signal under cable transmission conditions, including attenuation and frequency offset. The verification results demonstrate that our synchronizer functions properly, even when the signal is attenuated and subject to a frequency offset of up to 0.8 of the symbol rate. © 2023 IEEE.