MRCA 2.0: Area-Optimized Multi-grained Reconfigurable Cryptographic Accelerator for Securing Blockchain-based IoT Systems

This paper introduces a multi-grained reconfigurable cryptographic accelerator 2.0 (MRCA 2.0), upgrading from the first 8/32/64-bit CGRA named MRCA, to offer high performance with a smaller area and lower power consumption for blockchain-based IoT systems. To achieve these goals, we propose four innovative ideas: a dual processing element array (D-PEA) with reduced memories, a synchronous row connection and processing element (PE) architecture, a concatenable crypto ALU, and heterogeneous PEs. Our MRCA 2.0 has been successfully implemented on the TySOM-3A FPGA platform across 19 different algorithms. Our ASIC experiment on 45nm CMOS technology shows that MRCA 2.0 reduces area and power consumption by 1.6 and 1.4 times, respectively, compared to the previous MRCA. Compared to related works, MRCA 2.0 outperforms in throughput by 1.63-28.3 times and in energy efficiency by 1.6-3.4 times, while also offering better flexibility in supporting more 64-bit algorithms. © 1981-2012 IEEE.