LI-RV: A Fast and Efficient RISC-V based Coprocessor for Lightweight Cryptography

Hardware development for modern lightweight cryptography is essential to achieve high speed and low power consumption for IoT devices, where the RISC-V architecture with low-power, scalable, and configurable characteristics has been considered the most effective solution. Unfortunately, existing RISC-V designs for lightweight cryptography still suffer from low performance and hardware efficiency. To address this issue, we propose a RISC-V architecture, referred to as LI-RV, to handle various lightweight algorithms with enhanced performance and hardware efficiency. Particularly, LI-RV applies two key optimal ideas to achieve these goals, including dual ALUs and multi-level custom function units. Notably, LI-RV is the first RISC-V architecture utilizing dual concatenable 32-bit ALUs to perform two 32-bit parallel calculations or combine them to perform one 64bit calculation. Real-time performance evaluation on the ZCU102 FPGA shows that LI-RV provides a 1.7-3.0 times improvement in processing speed and a 1.6-2.5 times improvement in the power-delay product compared to the software implementation. Compared with related RISC-V designs, LI-RV outperforms them by 1.2-7.9 times in throughput. © 2024 IEEE.