A Compact SHA3 Implementation for Post-Quantum Cryptography

The SHA3 algorithm is essential for initializing symmetric primitives in post-quantum cryptography (PQC) algorithms. Mathematically, implementing SHA3 is straightforward with hardware. To ensure security, PQC algorithms select SHA3 based on the Keccak- f1600 permutation. Consequently, the SHA3 module is hardware-consuming and poses challenges for lightweight PQC implementations. This paper proposes a compact SHA3 hardware architecture for a case study of CRYSTALS-Kyber. Specifically, a configurable buffer is designed to perform padding, hashing, and holding data. Therefore, our design eliminates the need for costly padding and sampling FIFOs. The implementation results on the Artix-7 FPGA show that our design has a corresponding hardware consumption of 2828 LUTs, 1733 FFs, and 745 SLICEs. Compared to the reported-to-date implementations, our design saves up to 59% LUTs, 60% FFs, and 60% SLICEs. Our proposed SHA3 is wellsuited for lightweight PQC cryptosystems in resource-constrained IoT devices. © 2024 IEEE.