Low-Power Implementation of a High-Throughput Multi-core AES Encryption Architecture

Nowadays, the Internet of Things (IoT) has been a focus of research that improves and optimizes our daily life based on intelligent sensors and smart objects working together. Thanks to Internet Protocol connectivity, devices can be connected to the Internet, thus allowing them to be read, controlled, and managed at any time and at any place. Security and privacy are the key issues for deploying IoT applications, and still face some enormous challenges; especially, for devices that require high throughput and low latency as IoT cameras, IoT gateways, high-quality video conferencing systems... In this paper, we proposed a 10-cores AES hardware architecture to achieve high throughput. These cores shared KeyExpansion Block so this architecture has high efficiency in term of area and power consumption. Fully parallel, outer round pipeline technique is also used to achieve low latency. The design has been modelled in RTL VHDL and then synthesized with a 45nm CMOS technology using Synopsys Design Compiler. On the other hand, clock gating technique is used to save power consumption. We use PrimeTime tool (Synopsys) to estimate the power consumption. Implementation results show that the proposed architecture achieves a throughput of 853.8 Gbps at the maximum operating frequency of 667 MHz and clock gating technique allows more power savings. © 2020 IEEE.