Hybrid model in the block cipher applications for high-speed communications networks

The article proposes two different designs for the new block cipher algorithm of 128-bit block size and key lengths of 128-bit or 192-bit or 256-bit. The basic cipher round is designed in a parallel model to help improve the encryption/decryption speed. The differences of this design compared to the previous one developed on Switchable Data Dependent Operations (SDDOs) lies in the hybrid of the controlled elements (CEs) in the structure. Each design has a specific strength that makes the selection more compatible with the objectives of each particular application. The designs all meet the high security standards and possess the ability to fight off the attacks currently known. The designs match the limited environment of the wireless network by integrating effectively when implemented on Field-programmable gate array (FPGA) with both iterative and pipeline architectures for high effective integration. © 2020 Academy and Industry Research Collaboration Center (AIRCC).