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Low-complexity Check Node Processing for Trellis Min-max Nonbinary LDPC Decoding

Thi, H.P. and Tuan, H.D. and Trang Dang, L.D. and Lee, H. and Huu, T.N. (2018) Low-complexity Check Node Processing for Trellis Min-max Nonbinary LDPC Decoding. In: 11th International Conference on Advanced Technologies for Communications, ATC 2018, 18 October 2018 through 20 October 2018.

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Abstract

Nonbinary low-density-parity-check (NB-LDPC) code outperforms their binary counterpart in terms of error-correcting performance when the code length is moderate. Check node processing is a bottleneck of the NB-LDPC decoding. In this paper, a novel half-row modified two-extra-column trellis min-max (HR-mTEC-TMM) algorithm is proposed for the check node processing to reduce not only the complexity but also the storage memory. The check node unit (CNU) architecture corresponding to the proposed algorithm is designed for the (837, 726) NB-LDPC code over GF(32). The implementation results using 90-nm CMOS technology show that the proposed CNU architecture obtains a reduction of 28.3% for the area and 43.87% for the storage memory with an acceptable error-correcting performance loss, compared to existing work. © 2018 IEEE.

Item Type: Conference or Workshop Item (Paper)
Divisions: Faculties > Faculty of Information Technology
Faculties > Faculty of Radio-Electronic Engineering
Identification Number: 10.1109/ATC.2018.8587443
Uncontrolled Keywords: Decoding; Forward error correction; Check node units; Check nodes; Error-correcting; Layered decoding; Low density parity check; Min-max; Performance loss; VLSI design; Memory architecture
Additional Information: Conference code: 143867. Language of original document: English.
URI: http://eprints.lqdtu.edu.vn/id/eprint/9468

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