Dinh Ha, D. and Stempitsky, V. and Trung, T.T. (2017) Verilog-A based compact model of the silicon hall element. In: 7th International Conference on Integrated Circuits, Design, and Verification, ICDV 2017, 5 October 2017 through 6 October 2017.
ICDV-2017.pdf
Download (257kB) | Preview
Abstract
The paper describes the results of studies devoted to the development and testing of an electric (compact) Hall sensor model. The model implemented in Verilog-A hardware description language provides the capabilities of Hall sensor simulation in Cadence's software environment, taking into account temperature and other effects. Conducted testing of the model showed a satisfactory agreement between the data circuit simulation results of device-technological simulation. © 2017 IEEE.
| Item Type: | Conference or Workshop Item (Paper) |
|---|---|
| Divisions: | Faculties > Faculty of Radio-Electronic Engineering |
| Identification Number: | 10.1109/ICDV.2017.8188635 |
| Uncontrolled Keywords: | Circuit simulation; Computer software; Equivalent circuits; Field effect transistors; Hall effect transducers; Integrated circuits; Silicon; Compact model; Development and testing; Hall elements; Hall sensor; Software environments; Verilog-A; Computer hardware description languages |
| Additional Information: | Conference code: 133830. Language of original document: English. |
| URI: | http://eprints.lqdtu.edu.vn/id/eprint/9659 |
Actions (login required)
- View Item