Hoang, V.-P. and Nguyen, V.-T. and Nguyen, A.-T. and Pham, C.-K. (2017) A low power AES-GCM authenticated encryption core in 65nm SOTB CMOS process. In: 60th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2017, 6 August 2017 through 9 August 2017.
A low power AES-GCM authenticated encryption core in 65nm SOTB CMOS process..pdf
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Abstract
This paper presents a low power AES-GCM authenticated encryption IP core which combines an improved four-parallel architecture, an advanced 65nm SOTB CMOS technology and a low complexity clock gating technique. As a result, the power consumption of the proposed AES-GCM core is only 8.9mW which is lower than other AES-GCM IP cores presented in literature. The detail implementation results are also presented and discussed. © 2017 IEEE.
| Item Type: | Conference or Workshop Item (Paper) |
|---|---|
| Divisions: | Faculties > Faculty of Radio-Electronic Engineering |
| Identification Number: | 10.1109/MWSCAS.2017.8052873 |
| Uncontrolled Keywords: | Authentication; CMOS integrated circuits; Intellectual property core; Internet protocols; Parallel architectures; Authenticated encryption; Clock gating techniques; CMOS processs; CMOS technology; Low Power; Cryptography |
| Additional Information: | Conference code: 130955. Language of original document: English. |
| URI: | http://eprints.lqdtu.edu.vn/id/eprint/9692 |
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