Nguyen, V.-T. and Dao, V.-L. and Phan, T.-T.-D. (2016) Hardware implementation of cyclic codes error correction on FPGA. In: 3rd National Foundation for Science and Technology Development Conference on Information and Computer Science, NICS 2016, 14 September 2016 through 16 September 2016.
Hardware implementation of cyclic codes error correction on FPGA.pdf
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Abstract
This paper designs and implements a codec system using the Cyclic code on FPGA. The encoding system was based on the principle of dividing circuits and the decoding system was based on the principle of the Meggitt decoder. This work proposes the look-up table (LUT) method for the decoding system. The implementation results from FPGA show that the proposed decoding method has exactly resulted. In addition, the proposed cyclic decoder core using the look-up table method has lower resource and number of cycles compared to the cyclic decoder core using the Meggitt method. © 2016 IEEE.
| Item Type: | Conference or Workshop Item (Paper) |
|---|---|
| Divisions: | Faculties > Faculty of Radio-Electronic Engineering |
| Identification Number: | 10.1109/NICS.2016.7725675 |
| Uncontrolled Keywords: | Encoding (symbols); Error correction; Field programmable gate arrays (FPGA); Hardware; Table lookup; cyclic; Decoding methods; Decoding system; encode; Hardware implementations; Look up table; Look up table methods; Number of cycles; Decoding |
| Additional Information: | Conference code: 124536. Language of original document: English. |
| URI: | http://eprints.lqdtu.edu.vn/id/eprint/9798 |
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