Sai, V.-T. and Hoang, V.-P. (2016) An optimized implementation of logarithm hardware generator for digital signal processing. In: 6th IEEE International Conference on Communications and Electronics, IEEE ICCE 2016, 27 July 2016 through 29 July 2016.
An optimized implementation of logarithm hardware generator for digital signal processing.pdf
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Abstract
This paper presents an optimized hardware approximation of logarithm function for digital signal processing systems. The proposed method combines the multi-segment linear approximation with a small look-up table and an optimization algorithm to trade-off the computation speed with the hardware complexity. As a result, an efficient logarithm generator with simple structure and high computation speed is presented. The implementation results are also discussed. © 2016 IEEE.
| Item Type: | Conference or Workshop Item (Paper) |
|---|---|
| Divisions: | Faculties > Faculty of Radio-Electronic Engineering |
| Identification Number: | 10.1109/CCE.2016.7562628 |
| Uncontrolled Keywords: | Application specific integrated circuits; Approximation algorithms; CMOS integrated circuits; Digital signal processing; Economic and social effects; Hardware; Optimization; Reconfigurable hardware; Table lookup; Digital signal processing systems; Hardware complexity; High computation speed; Linear approximations; logarithm generator; Low Power; Optimization algorithms; Optimized implementation; Signal processing |
| Additional Information: | Conference code: 123684. Language of original document: English. |
| URI: | http://eprints.lqdtu.edu.vn/id/eprint/9811 |
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