Dao, V.-L. and Hoang, V.-P. and Nguyen, A.-T. and Le, Q.-M. (2016) A compact, low power AES core on 180nm CMOS process. In: 2016 IEEE Joint Conference on International Conference on IC Design and Technology, ICICDT 2016 and Solid State Systems Symposium, 4S 2016, 27 June 2016 through 29 June 2016.
A compact, low power AES core on 180nm CMOS process.pdf
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Abstract
This paper presents a compact, low power AES cryptography core with a small S-box and an improved key expansion block for emerging wireless networks. The implementation results with an 180nm CMOS standard library show that the proposed AES core can reduce the area and power consumption significantly. © 2016 IEEE.
| Item Type: | Conference or Workshop Item (Paper) |
|---|---|
| Divisions: | Faculties > Faculty of Radio-Electronic Engineering |
| Identification Number: | 10.1109/ICICDT.2016.7542040 |
| Uncontrolled Keywords: | Application specific integrated circuits; CMOS integrated circuits; Cryptography; CMOS processs; Emerging wireless networks; Key expansion; Low area; Low Power; Standard libraries; Low power electronics |
| Additional Information: | Conference code: 123345. Language of original document: English. |
| URI: | http://eprints.lqdtu.edu.vn/id/eprint/9818 |
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