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Simplified Variable Node Unit Architecture for Nonbinary LDPC Decoder

Pham Thi, H. and Dinh The, C. and Pham Xuan, N. and Dao Tuan, H. and Lee, H. (2019) Simplified Variable Node Unit Architecture for Nonbinary LDPC Decoder. In: 15th Annual IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2019, 11 November 2019 through 14 November 2019.

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Abstract

Nonbinary low-density-parity-check (NB-LDPC) code outperforms their binary counterpart in terms of error-correcting performance and error-floor property when the code length is moderate. However, the drawback of NB-LDPC decoders is high complexity and the complexity increases considerably when increasing the Galois-field order. In this paper, a simplified basic-set trellis min-max (sBS-TMM) algorithm that is especially efficient for high-order Galois Fields, is proposed for the variable node processing to reduce the complexity of the variable node unit (VNU) as well as the whole decoder. The decoder architecture corresponding to the proposed algorithm is designed for the (837, 726) NB-LDPC code over GF(32). The implementation results using 90-nm CMOS technology show that the proposed decoder architecture reduces the gate count by 21.35% and 9.4% with almost similar error-correcting performance, compared to the up-to-date works. © 2019 IEEE.

Item Type: Conference or Workshop Item (Paper)
Divisions: Faculties > Faculty of Radio-Electronic Engineering
Identification Number: 10.1109/APCCAS47518.2019.8953111
Uncontrolled Keywords: Decoding; Errors; Forward error correction; Basic-set; Decoder architecture; Error-correcting; Low density parity check; Min-max; Non-binary ldpc; Variable node units; VLSI design; Memory architecture
Additional Information: Conference code: 156723. Language of original document: English.
URI: http://eprints.lqdtu.edu.vn/id/eprint/9224

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