Le Duc, H. and Hoang, V.-P. and Nguyen, D.-M. and Pham, C.-K. (2018) Hardware Implementation of Background Calibration Technique for TIADCs with Signals in Any Nyquist Bands. In: 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018, 27 May 2018 through 30 May 2018.
Hardware Implementation of Background Calibration Technique for TIADCs with Signals in Any Nyquist Bands..pdf
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Abstract
We investigate a novel fully digital background calibration technique to mitigate the gain and timing mismatches in Time-Interleaved Analog-to-Digital Converters (TIADCs) for the wideband bandlimited input signal at any Nyquist zones. The correction scheme is simple by subtracting the image signals from the distorted signal. The channel mismatch parameters are estimated based on out-of-band error estimation. Neither an additional reference channel and nor a pilot input are required in calibration. A four-channel 60dB SÒR TIADC operating at 2.7GHz is used in both simulation and experimental implementation to validate the proposed calibration technique. The SNDR improvement is 16dB for a multi-tone input occupied at the third Nyquist band. The calibration method is validated on Altera FPGA DE4 board. In a Hardware-In-the-Loop emulation framework, the synthesized circuit works effectively and utilizes a very little amount of the hardware resource in the FPGA chip. © 2018 IEEE.
Item Type: | Conference or Workshop Item (Paper) |
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Divisions: | Faculties > Faculty of Radio-Electronic Engineering |
Identification Number: | 10.1109/ISCAS.2018.8351116 |
Uncontrolled Keywords: | Analog to digital conversion; Calibration; Field programmable gate arrays (FPGA); Background calibrations; Calibration method; Calibration techniques; Digital background calibration; Hard-ware-in-the-loop; Hardware implementations; Reference channels; Time-interleaved analog to digital converters; Hardware |
Additional Information: | Conference code: 141792. Language of original document: English. |
URI: | http://eprints.lqdtu.edu.vn/id/eprint/9569 |