Hoang, V.-P. and Dao, V.-L. and Pham, C.-K. (2016) An ultra-low power AES encryption core in 65nm SOTB CMOS process. In: 13th International SoC Design Conference, ISOCC 2016, 23 October 2016 through 26 October 2016.
An ultra-low power AES encryption core in 65nm SOTB CMOS process.pdf
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Abstract
This paper presents an efficient ASIC implementation of the low area and ultra-low power AES encryption core with an optimized S-box, Rcon and control blocks optimization, combined with a simple clock gating technique using an ultra-low power 65nm SOTB CMOS technology. The ASIC implementation results show that the proposed AES encryption core requires a small number of clock cycles with ultra-low power consumption and achieves higher resource usage efficiency compared with other designs. © 2016 IEEE.
| Item Type: | Conference or Workshop Item (Paper) |
|---|---|
| Divisions: | Faculties > Faculty of Radio-Electronic Engineering |
| Identification Number: | 10.1109/ISOCC.2016.7799747 |
| Uncontrolled Keywords: | Clocks; CMOS integrated circuits; Energy efficiency; AES encryption; Clock gating techniques; CMOS technology; Control blocks; Number of clock cycles; Resource usage; Ultra low power; Ultra-low power consumption; Cryptography |
| Additional Information: | Conference code: 125690. Language of original document: English. |
| URI: | http://eprints.lqdtu.edu.vn/id/eprint/9767 |
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